DFT TEST TECHNIQUES


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DFT TEST TECHNIQUES
DFT TEST TECHNIQUESWith the advances made in DFT a lot of test capability is built into the SoC device itself. A very important key to this is the processing power in the device. And with logic gate densities doubling every 24 months following Moore's, chip designers have been adding test-related circuitry to the device and in some cases redundant copies of a circuit, cell, or core on the same die. This is a technique that has been in use in memory design for many years. Also, with this extra space, built-in self-test and design configuration circuitry can be employed on silicon for self-diagnosis. If the BIST and design circuitry can do all the testing, and the circuitry is working as designed, there is less need for ATE in terms of the accuracy and fidelity needed for testing the SoC device. T…
Citation
Hwaiyu Geng, CMfgE, PE: Semiconductor Manufacturing Handbook, Second Edition. DFT TEST TECHNIQUES, Chapter (McGraw-Hill Professional, 2018 2005), AccessEngineering Export