ARCHITECTURE OF A SOC TESTER


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ARCHITECTURE OF A SOC TESTER
ARCHITECTURE OF A SOC TESTERBecause the SoC device contains microprocessor, memory, analog blocks, high- and low-speed external interfaces, and wireless the tester for these devices consist of test hardware from each of the tester architectures described so far. To efficiently test the high volume of SoC devices in production, the ATE architecture has evolved to a tester in the test head consisting of different type test modules or instruments. The mainframe of the tester just houses the system computer, site controllers cooling, and power needed for the rest head electronics. The site controllers offload tester-related activities from the system computer and is used in production ATE to improve test throughput. Figure …
Citation
Hwaiyu Geng, CMfgE, PE: Semiconductor Manufacturing Handbook, Second Edition. ARCHITECTURE OF A SOC TESTER, Chapter (McGraw-Hill Professional, 2018 2005), AccessEngineering Export