ARCHITECTURE OF A FLASH MEMORY TESTER


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ARCHITECTURE OF A FLASH MEMORY TESTER
ARCHITECTURE OF A FLASH MEMORY TESTERThe typical flash memory tester architecture is shown in Fig. 21.12 and will be described in this section. Because flash memory consists of millions of similar FETs that require a similar algorithm to test, the APG allows the manufacturer to create an algorithm for one FET and then simply set up ranges for the amount of rows, columns, and blocks (X, Y, and Z address generators) to test. Crossover or scrambling circuitry is needed to map the address generators to the correct address pins because flash memory devices have different numbers of rows, columns and blocks, circuitry. Parametric measurement units
Citation
Hwaiyu Geng, CMfgE, PE: Semiconductor Manufacturing Handbook, Second Edition. ARCHITECTURE OF A FLASH MEMORY TESTER, Chapter (McGraw-Hill Professional, 2018 2005), AccessEngineering Export