PHYSICAL DESIGN SOLUTIONS FOR 3D IC


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PHYSICAL DESIGN SOLUTIONS FOR 3D IC
PHYSICAL DESIGN SOLUTIONS FOR 3D ICIn this section, we provide the state-of-the-art solutions in the literature to address each of the design challenges discussed in Section 0.
3D Placement Algorithms The most straightforward method for 3D placement follows a divide-and-conquer methodology. This method first partitions the gate-level circuit netlist into different layers while minimizing the number of interlayer cuts (e.g., using partitioning algorithms such as Fiduccia-Mattheyses3), and then performs regular 2D placement in each of the layers sequentially.
Citation
Hwaiyu Geng, CMfgE, PE: Semiconductor Manufacturing Handbook, Second Edition. PHYSICAL DESIGN SOLUTIONS FOR 3D IC, Chapter (McGraw-Hill Professional, 2018 2005), AccessEngineering Export