PHYSICAL CHALLENGES AND PHYSICAL DESIGN TOOLS FOR 3D IC


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PHYSICAL CHALLENGES AND PHYSICAL DESIGN TOOLS FOR 3D IC
PHYSICAL CHALLENGES AND PHYSICAL DESIGN TOOLS FOR 3D IC3D IC's physical design is a crucial step that translates a circuit abstraction (i.e., a flat circuit netlist) into an actual layout. 3D physical design tools face several unique challenges, and in this section we focus on some of the key challenges, including challenges in 3D placement, clock tree synthesis, thermal management, power delivery, and reliability concerns.
3D Placement For a given standard cell netlist, the 3D placement problem aims to find the location for each logic gate in the 3D space, such that the total wire length is minimized and the usage of TSVs is under control.
Citation
Hwaiyu Geng, CMfgE, PE: Semiconductor Manufacturing Handbook, Second Edition. PHYSICAL CHALLENGES AND PHYSICAL DESIGN TOOLS FOR 3D IC, Chapter (McGraw-Hill Professional, 2018 2005), AccessEngineering Export