Effects of Dwell Time and Ramp Rate on SAC Thermal Cycling Test Results


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Effects of Dwell Time and Ramp Rate on SAC Thermal Cycling Test Results
1010608Effects of Dwell Time and Ramp Rate on SAC Thermal Cycling Test Results
<emphasis role="bold">Introduction</emphasis> For either reliability testing and data analysis or design for reliability (DFR) of lead-free interconnects, the most common loading condition is the temperature cycling [
Citation
John H. Lau: Reliability of RoHS-Compliant 2D and 3D IC Interconnects. Effects of Dwell Time and Ramp Rate on SAC Thermal Cycling Test Results, Chapter (McGraw-Hill Professional, 2011), AccessEngineering Export